0.5V design ecosystem
CSEM, a leader in ultra-low-power ASIC design, and Mie Fujitsu Semiconductor (MIFS), a leading wafer foundry, have joined forces to develop a near-threshold 0.5V ecosystem; since energy scales with the square of the supply voltage, huge reductions in energy consumption can be achieved for similar performance. MIFS’ Deeply Depleted Channel (DDC) technology is perfectly adapted to low-power applications, while its immunity to random dopant fluctuations makes it suitable for low-voltage operation. Low-voltage operation, however, is still subject to process and temperature and other variations. To overcome the impact from these variations CSEM and MIFS applied a variety of design techniques and implemented Body-bias-based Adaptive Dynamic Frequency Scaling (ADVbbFS) as one of the key IPs.
A 32-bit RISC microcontroller designed in C55DDC was presented recently at IEEE CICC in Austin, TX, demonstrating only 2.5uW/MHz—a new world record in a 55nm CMOS process.
For Keizaburo Yoshie, Senior Vice-President, MIFS, “Combining CSEM’s ULP design experience with MIFS’ DDC process technology helps realize IOT chip designs that are unbeatable in energy efficiency.” Alain-Serge Porret, CSEM’s Vice-President, Integrated & Wireless Systems, says, “Low-voltage design is essential for the next generation of IOT devices; we were delighted to team up with MIFS to make this dream a reality.”