The conflicting requirements of increased miniaturization along with longer battery life mean that standard CMOS technologies are reaching their limits and that new solutions are urgently needed. Since the power consumption of digital circuits is proportional to the square of the supply voltage, low voltage operation is the best hope for significant improvements while maintaining NRE costs in check.
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To allow devices to operate at low voltage level such as 0.5V, CSEM has integrated a complete SoC using the Deeply Depleted Channel (DDC) technology developed in cooperation with Mie Fujitsu Semiconductor Ltd (MIFS), a Japanese semiconductor foundry. The test-chip shows that a factor of 3-5x in energy can be gained by combining optimized libraries and proper design techniques. It fits particularly with trends identified last year at Electronica especially in future IoT applications where power efficiency is a killer.
Indeed, the recently released Extreme-Low Power (ELP) platform with the associated ecosystem is now available and allows designers to develop the next generation of low energy and self-powered SoCs. The test-chip developed as a SoC and used in the demonstrator, is able to show the stability of the frequency over the process corners when the closed-loop biasing is used and even with temperature variation.
Deeply Depleted Channel (DDC) technology enables fabrication of extremely-low-leakage transistors operating at supply voltages (Vdd) below 0.5V to obtain maximum power efficiency. DDC offers a better Vt mismatch & spread than conventional CMOS, allowing lower Vdd with minimum degradation of performance. Applying DDC to 40/55nm CMOS along with mixed signal/RF and embedded NVM allows cost-effective and highly integrated analog and RF SoCs for IoT/wearable platforms.
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