CSEM has also done a number of projects using RISC-V processors, one of which is the customization of a processor to reduce the power consumption so that it can be implemented in an autonomously powered wireless wearable device. The project resulted in an industry grade core with 3.2 CoreMark/MHz and 2.23uW/MHz in a 22nm process.

Why RISC-V?

RISC-V  is an open standard instruction set architecture (ISA), which is quickly gaining popularity and is now a viable alternative for ARM, certainly in low power applications, such as Edge computing and IoT.

The benefit of the RISC-V open standard is that companies implementing processors on their SoCs have much more freedom to decide whether they develop in-house, use open source, or buy propriatary cores, and have a much wider range of support/service models and possibilities for customizations than is the case in other ISA eco-systems. RISC-V has reduced significantly the problem of 'Vendor lock-in', and open-source implementations have even eliminated this process completely.

CSEM offers

• Selection of the most suitable processor for your project
• Customization of RISC-V cores to your specific use case
• Seamless and Industry grade integration into a custom ASIC
  Compatible with debugging and tracing tools such as IAR, Segger, Lauterbach and open-source tools
  Deep expertise and IP for security / RTOS / AI accelerators / Bluetooth / energy harvesting / analog / RF
• Full SoC design and verification

CSEM is the perfect partner for short time-to-market projects where you:

• implement a processor on your SoC for the first time, or;
• need a smooth transition from another ISA eco-system to the RISC-V ecosystem, or;
• have very challenging low power requirements

Supported processors

CSEM supports a wide range of processors from ultra low power 32bit to high performance 64bit processors

• CSEM’s IcyFlex-V
• OpenHW: CV32E40P & CVA6
• lowRISC
• SweRV

Other on request

Related Information

icyFlex-V – CSEM's low power RISC-V processor